ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.top/obj/xsim_22.c. 에러 고치기
2024. 9. 2. 20:53ㆍSystem Verilog
Vivado Simulator v2024.1
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /tools/xilinx/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab top -L uvm -timescale 1ns/1ps
Multi-threading is on. Using 14 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4468] File : /proj/xbuilds/SWIP/2024.1_0404_1523/installs/lin64/Vivado/2024.1/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv, Line : 25994, RANDC variable size more than 8 bits. This will be treated as a RAND variable instead.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package uvm.uvm_pkg
Compiling package std.std
Compiling package work.yapp_pkg
Compiling package work.$unit_yapp_pkg_sv_3228151111
Compiling module work.yapp_if_default
Compiling module work.host_ctl_default
Compiling module work.port_fsm
Compiling module work.fifo
Compiling module work.yapp_router
Compiling module work.top
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/work.top/obj/xsim_22.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...
해당 Error가 나면, xelab옵션에 -cc clang 을 주면 해결된다.
#!/bin/zsh
xvlog -f file_list.f \
-sv \
-L uvm \
-d UVM_VERBOSITY=UVM_LOW
xelab top -L uvm -timescale 1ns/1ps -cc clang
# -v 2 옵션을 주면 자세한 로그를 볼 수 있다.
xsim top -t log_wave.tcl -wdb dump.wdb -view dump.wdb -gui
출처 :
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